1. Technical Field
The present disclosure relates to a display. More particularly, the present disclosure relates to a display panel and a structural design of a non-display area thereon.
2. Description of Related Art
In recent years, technology related to display devices has improved significantly. Digital display panels have the advantages of compact size, low cost and high performance. Components within digital display panels are highly integrated using advanced processes, so as to achieve optimal display quality in a small size and with a low total cost.
For example, the Chip-On-Glass (COG) packing technique is utilized to place the integrated circuit (IC) of a digital display panel directly onto a glass substrate. Due to the high resolution of modern display panels, the integrated circuit used therein must accommodate a significant number of pins utilizing a small packing space and thickness. The Chip-On-Glass packing technique eliminates the need for a substrate or copper foil used in a traditional packing technique. Therefore, with the use of the Chip-On-Glass packing technique, the overall thickness of the display device can be reduced, and this is in line with recent trends toward reduced profiles for display panels and contributes to higher resolution in modern display panels.
With the present Chip-On-Glass packing technique, a driving integrated circuit for the display panel is integrated onto a non-display area located on the edges of the display panel. The driving integrated circuit is electrically connected to signal pads on the non-display area. Electronic signals are conducted from the signal pads via metal signal traces to the display area of the display panel, in order to drive the display-driving units (e.g., thin film transistors, TFTs) within the display area.
Reference is made to FIG. 1A, which is a sectional diagram illustrating a non-display area within a traditional display panel. As shown in FIG. 1A, there are several signal pads 102 disposed on a substrate 100. Transparent conductive layers 108, e.g., Indium Tin Oxide (ITO) conductive layers, are disposed on the signal pads 102. With the use of traditional solutions, an integrated circuit (not shown) is connected to the conductive layers 108 through metal bumps 120 (e.g., IC bumps), and is further electrically connected with the signal pads 102.
In an ideal case, during the manufacturing process, these IC bumps (i.e., metal bumps 120) press down conductive particles 110 toward the conductive layers 108 above the signal pads 102, so as to complete the electrical connection as shown in FIG. 1A. FIG. 1B and FIG. 1C are sectional diagrams illustrating the traditional display panel when some shifting errors occur during manufacture.
As shown in FIG. 1B, a metal signal trace 104 can be disposed between two signal pads 102. If a shifting error occurs when the IC bumps 120 are pressed downward, the conductive particles 110 may be pressed to penetrate the isolation structure (e.g., a gate isolation layer 106a and a passivation layer 106b) above the metal signal trace 104, such that the metal signal trace 104 is short-circuited to the signal pad 102. In order to prevent the conductive particles 110 from penetrating the isolation structure, the tolerance range of the Chip-On-Glass packing technique is set so that there is no overlapping with the area above the metal signal traces 104. Hence, the tolerance range with the conventional Chip-On-Glass packing technique is extremely limited.
In another case as shown in FIG. 1C, a beaded drainage may be formed by several conductive particles 110, and as a result, two signal pads 102 can be short-circuited via the beaded drainage.